This invention relates to signal detect circuitry for a high-speed serial interface, especially in a programmable device.
Programmable integrated circuit devices, such as programmable logic devices (PLDs), frequently incorporate high-speed serial interfaces to accommodate high-speed (greater than 1 Gbps) serial I/O standards, which operate at data rates of up to 6 Gbps or higher. Each high-speed serial interface may include one or more transceivers.
Each transceiver typically includes signal detection circuitry in both its receiver and transmitter portions. In the receiver portion, the signal detection circuitry typically is referred to as “signal detect” or “SD,” and generates a signal that alerts the rest of the receiver to incoming data. In the transmitter portion, the signal detection circuitry typically is referred to as “receiver detect” or “RxD,” and generates a signal when it detects that transmitted signals are being received by a receiver at the other end.
Known signal detection circuits are analog, and typically incorporate a rectifier and an integrator, which produce a signal that is detected by a sense amplifier and then compared to a reference level by a high-speed peak detector utilizing a voltage-follower configuration. The voltage follower is designed such that the charge current is much higher than the discharge current. This can lead to static offsets. As an analog circuit, the signal detector may be subject to variations in process, temperature and/or supply. In addition, the sense amplifier may need to have a large bandwidth, making it difficult to design for higher data rates.